Fabrication of integrated circuits with borderless vias

Abstract

A method of forming interconnecting layers in a semiconductor device is such that, whereby even if a via is misaligned with a metal line, a portion of the via not enclosed by the metal is enclosed by an etch stop spacer. In addition, the via is always capped by the metal even if borders are not used in the design of the device. A metal layer is formed atop the foundation layer to cover the boundary layer, including completely filling the trench with metal. A protection layer is then formed on the surface of the metal layer. The protection layer and the metal layer are patterned to define a line of composite protection/metal on the surface of the foundation layer while leaving a remaining portion of the metal layer exclusive of the metal of the line. An etch stop layer is formed which substantially conforms to the shape of the line and to the remaining portion of the metal layer. Selected portions of the etch stop layer are removed to expose the protection surface of the line, and to leave etch stop spacers conforming to at least one sidewall portion of the line while exposing a sub-portion of the remaining portion of the metal layer. The exposed sub-portion of the metal layer is removed to expose a portion of the boundary layer, then the exposed portion of the boundary layer is removed. A layer of via dielectric is formed that covers and extends above the line. A portion of the via dielectric layer above the line is removed to expose a portion of the protection surface of the line. Finally, at least a portion of the protection surface is removed from the line, leaving the metal portion of the line only.