Scsi host adapter integrated circuit utilizing a sequencer circuit to

Abstract

A single chip circuit is used in combination with a host system microprocessor to provide host-adapter functions for a SCSI interface. The host adapter integrated circuit includes a 128 byte DMA FIFO, a 8 byte SCSI FIFO, hardwired automatic sequencers for the SCSI ARBITRATION and SELECTION phases, hardware interrupt generating circuitry, two clock sources, a register set and a powerdown capability. The host computer system microprocessor is used to perform selected SCSI phases. Other SCSI phases are performed automatically by the integrated circuit of this invention. When a delay in a SCSI phase is anticipated, according to the principles of this invention control of the microprocessor is returned to the host computer system. Hence, the microprocessor may execute a user application while the integrated circuit simultaneously performs one or more SCSI phases. When the SCSI phase is complete or other predetermined conditions occur on the SCSI bus, a hardware interrupt is sent to the microprocessor. In response to the interrupt, the microprocessor is available to support further SCSI operations by the integrated circuit of this invention.