The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 05, 1997
Filed:
Nov. 13, 1995
Wayne P Dupree, Midland, MI (US);
Stephen G Churchill, Midland, MI (US);
Jeffry R Gallant, Midland, MI (US);
Larry A Root, Midland, MI (US);
William J Bressette, Saginaw, MI (US);
Robert A Orr, III, Midland, MI (US);
Srikala Ramaswamy, Midland, MI (US);
Jeffrey A Lucas, Midland, MI (US);
James A Bleck, Midland, MI (US);
The Dow Chemical Company, Midland, MI (US);
Abstract
A massively multiplexed central processing unit ('CPU') which has a plurality of independent computational circuits, a separate internal result bus for transmitting the resultant output from each of these computational circuits, and a plurality of general purpose registers coupled to each of the computational circuits. Each of the general purpose registers have multiplexed input ports which are connected to each of the result buses. Each of the general purpose registers also have an output port which is connected to a multiplexed input port of at least one of the computational circuits. Each of the computational circuits are dedicated to at least one unique mathematical function, and at least one of the computational circuits include at least one logical function. At least one of the computational circuits includes a plurality of concurrently operable mathematical and logical processing circuits, and an output multiplexer for selecting one of the resultant outputs for transmission on its result bus. The CPU also features a very long instruction word which uses a series of assigned bit locations to represent the selections codes for each of the CPU components. These selection codes are directly transmitted to each of the CPU components by a program control circuit. A separate data control circuit is further provided in achieve a Harvard architecture design for the CPU.