The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 05, 1997

Filed:

May. 01, 1996
Applicant:
Inventors:

Tomio Suzuki, Hyogo, JP;

Motoko Hara, Hyogo, JP;

Shigeru Mori, Hyogo, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C / ;
U.S. Cl.
CPC ...
36518905 ; 365201 ; 365233 ;
Abstract

A semiconductor memory device is provided which can apply a voltage stress to every adjacent bit lines even when data is written using a data bit compression function in a burn-in test mode. More specifically, when data is written using the data bit compression function in the test mode, an input buffer circuit is brought to a state in which it receives a signal corresponding to a signal dq0 applied to a specific input/output terminal by a switch circuit controlled by a test mode specify signal TE in common. When an inversion designate signal INV is in an active state, a complementary signal corresponding to a signal obtained by inversion of signal dq0 by an inverting circuit is output to internal data buses IO0, ZIO0, and IO2, ZIO2. On the other hand, a complementary signal corresponding to signal dq0 is output to internal data buses IO1, ZIO1, and IO3, ZIO3.


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