Apparatus and method for extending data retention time of semiconductor

Abstract

In halt period during standby time, a cell plate node potential switching circuit changes the potential of a cell plate node to a low potential that is lower than a high potential adopted in a burst refresh operation. As a result, a potential difference between both ends of a PN junction of a memory cell transistor is decreased, thereby suppressing a leakage current flowing through the PN junction. Simultaneously, a word driver circuit changes the potential of a word line to a negative potential that is lower than a normal potential adopted in the burst refresh operation. As a result, an off state of the memory cell transistor is enhanced owing to decrease of a gate-source voltage thereof, thereby suppressing a leakage current flowing from the bit line to a charge storage node. Accordingly, a leakage current flowing through the PN junction of the memory cell transistor and a leakage current flowing from the bit line through the memory cell transistor to the charge storage node are both suppressed during the standby time. Thus, a refresh interval is elongated so as to decrease power consumption.