The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 05, 1997
Filed:
Jul. 11, 1995
Applicant:
Inventors:
Bradley R Roetcisoender, Kirkland, WA (US);
Yongtao You, Bellevue, WA (US);
Richard K McGehee, Bellevue, WA (US);
Assignee:
Cascade Design Automation Corporation, Bellevue, WA (US);
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F / ;
U.S. Cl.
CPC ...
364490 ; 364488 ; 364489 ; 364491 ;
Abstract
A method and apparatus for determining the layout of an integrated circuit, in accordance with timing constraints, by means of sizing the buffers in the layout. A nominal netlist for the layout of the integrated circuit is used to determine critical paths through the circuit. The time-critical paths are determined and the instances of the buffers along the path are resized so that the time delays in the time-critical paths are either brought within the predetermined timing criteria, or no further improvement in any time-critical path is possible.