The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 05, 1997
Filed:
Nov. 07, 1996
Neil Davies, Sonnenbuehl-Genkingen, DE;
Robert Bosch GmbH, Stuttgart, DE;
Abstract
An integrated circuit having a gate oxide, preferably for a DMOS circuit having a protective device against electrostatic overvoltages (ESD), is to connect a limiting circuit in series with the protective device. This series circuit means that, during the wafer production, an increased voltage can be applied to the gate of the integrated circuit, for testing the gate oxide, without the circuit being limited to a lower value. After testing, the limiting circuit is connected irreversibly in its low-resistance state, with the result that subsequent ESD interference voltages are limited by the built-in protective device. A zener zapping diode is provided as the limiting circuit. An advantageous result of the arrangement is the fact that an additional bonding connection for connecting the gate connection to the protective device is no longer necessary.