The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 05, 1997

Filed:

Jun. 30, 1994
Applicant:
Inventors:

Charles R Patton, Murietta, CA (US);

John R Edwards, Mountain View, CA (US);

Anil Sareen, Mission Viejo, CA (US);

Assignee:

Western Digital Corporation, Irvine, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G11B / ;
U.S. Cl.
CPC ...
360 75 ; 360 60 ; 318601 ; 318635 ;
Abstract

A disk drive for operating in an environment in which the drive is subject to physical shock includes a circuit which senses movement of a transducer head support arm which result from a shock's rotational component. The rotational shock is detected as a residual BEMF signal in the drive's VCM coil winding. The residual signal is extracted from much larger position control signals that are applied to the VCM winding during normal system operation by providing circuits that simulate the VCM winding voltage caused by the position control signal and subtracting the outputs of the simulation circuits from the actual VCM coil winding voltage. This eliminates the normal operating components and leaves a residual signal that represents only the small portion of the VCM BEMF signal that results from the rotational shock. A threshold circuit compares the shock BEMF signal to a predetermined threshold. If the BEMF signal exceeds the threshold, disk drive write operations are aborted. An active calibration system is also employed that regularly updates both the simulated resistance and simulated inductance to null out the effects of temperature, design and aging tolerances.


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