The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 05, 1997

Filed:

May. 31, 1994
Applicant:
Inventor:

Takumi Miyashita, Kawasaki, JP;

Assignee:

Fujitsu Limited, Kawasaki, JP;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H03M / ;
U.S. Cl.
CPC ...
341122 ;
Abstract

The present invention is intended to realize an analog signal sampling circuit constructed with field-effect transistors wherein errors caused by parasitic capacitance or gate conductance in a switch device is reduced. The sampling circuit of the invention comprises an inverting amplifier, a capacitor, a first switch for selecting a reference voltage Vref or a target signal Vin for input to the capacitor, and a second switch for opening or closing the connection between the input and output of the inverting amplifier, and produces an output in proportion to the difference between the target signal Vin and reference voltage Vref held in the capacitor, the sampling circuit being characterized by the inclusion of a voltage converting circuit whereby the operating voltage of the clock signal applied to the gate of the field-effect transistor forming the second switch is converted to a voltage related to the self-bias level of the inverting amplifier.


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Miyashita, Takumi. (1997). Analog signal sampling circuit constructed with field-effect transistors (U.S. Patent No. 5654709). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/5654709

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