Non-glitch clock switching circuit

Abstract

A clock switching circuit responsive to at least one clock select signal switches to a selected one of a plurality of clock signals while minimizing transients generated during the switching. The circuit includes at least one flip-flop receiving a corresponding one of the at least one clock select signal; a plurality of flip-flops individually receiving an output of a corresponding one of the at least one flip-flop, and an inverted version of a corresponding one of the clock signals; a plurality of AND gates individually receiving the output of a corresponding one of the at least one flip-flop, the output of a corresponding one of the plurality of flip-flops, and a corresponding one of the plurality of clock signals; and an OR gate receiving the outputs of the AND gates so that the selected one of the plurality of clock signals is provided at an output of the OR gate, and fed back to an inverted clock input of the at least one flip-flop. Timing of the clock switching circuit is such that a first clock signal is provided to the circuit until a first falling edge of the first clock signal occurs following an indication to change clock signals, and a second clock signal is provided to the circuit after a first falling edge of the second clock signal occurs following the first falling edge of the first clock signal following the indication to change clock signals.