The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 29, 1997
Filed:
Oct. 24, 1995
Mark W Jennion, Chester Springs, PA (US);
Joseph H Fell, III, East Fallowfield, PA (US);
Paul H Selby, III, Norristown, PA (US);
Joseph J Scorsone, Broomall, PA (US);
Unisys Corporation, Blue Bell, PA (US);
Abstract
An improved load board design having a generic test circuit integrated into the load board capable of functioning with varying devices under test and requires little to no wiring. The test circuit is located in a fixed and optimal position of the load board with relation to the DUT. In a preferred embodiment, the test circuit is a quiescent test circuit for interfacing an integrated circuit tester to the DUT. The quiescent test circuit is capable of supplying high powered voltage to a DUT while the DUT's desired internal state is reached. At this point, the integrated circuit tester, sends an active select signal to the quiescent test circuit instantaneously deselecting the high-powered voltage supply to the DUT and selecting the integrated circuit tester's parametric measurement unit for powering the DUT. The integrated circuit tester, through a parametric measurement unit is capable of measuring the quiescent current of the DUT, while powering the DUT.