Guided transfers with variable stepping

Abstract

This invention is a manner of control of the addresses of memory accesses. The data processing device of this invention includes a memory, a control circuit, a guide table and an address generating circuit. The control circuit receives a packet transfer request and packet transfer parameters. The packet transfer parameters include a start address, a number of guide table entries and a table pointer. The guide table includes guide table entries, each guide table entry having an address value and dimension values defining a block of addresses. The table pointer initially points to a first guide table entry in the guide table. The address generating circuit forms a set of block of addresses for memory access corresponding to each guide table entry, having a start address from a predetermined combination of the start address and the address value of the guide table entry. The block of addresses are formed from the dimension values. Following the memory accesses, the address generating circuit updates the table pointer to point to a next entry in the guide table. The address generating circuit may optionally form the predetermined combination of starting address and address value of guide table entry by adding the address value to the prior block starting address or by adding the guide table value to the starting address. The memory access may be a memory read from the block of addresses or a memory write to the block of addresses. In the preferred embodiment, memory, a data processor and a data transfer controller performing the above memory accesses is constructed in a single semiconductor chip. The data transfer controller may access external memory in the same manner as on-chip memory.