The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 22, 1997
Filed:
Jan. 17, 1996
Kristann L Moody, Barrington, NH (US);
Ravi Vig, Bow, NH (US);
P Karl Scheller, Rochester, NH (US);
Jay M Towne, Andover, NH (US);
Teri L Tu, Bow, NH (US);
Allegro Microsystems, Inc., Worcester, MA (US);
Abstract
A Hall transducer produces a signal Vsig. Threshold voltages V.sub.Pth and V.sub.Nth are generated at the beginning, t.sub.update, of each of a succession of update time intervals, of 64 pulses in Vsig, to be fixed percentages respectively of the peak to peak voltage in Vsig. A proximity-detector binary output voltage is high when Vsig exceeds threshold voltage V.sub.Pth and low when Vsig is below threshold voltage V.sub.Nth. Signals V.sub.Pold and V.sub.Nold, generated by first and second DACs, are equal to the first positive and negative peaks in Vsig after each time t.sub.update initiating the start of a successive interval. Signals V.sub.Pnew and V.sub.Nnew, simultaneously generated by third and fourth DACs, are equal to the greatest positive and negative peak voltages in Vsig during the interval ending at t.sub.update. Counters present their count to the first and second DACs that count pulses from a clock for tracking and holding +/- peaks in Vsig. After each time t.sub.update, a pulse in a signal Vupdt is generated if at time t.sub.update V.sub.Nnew lies outside the range. V.sub.Nold -v to V.sub.Nold +v of if V.sub.Nnew lies outside the range V.sub.Nold -v to V.sub.Nold +v, where v is an incremental DC bias voltage. Vupdt resets the counters so that during the succeeding update time interval the threshold voltages V.sub.Pth and V.sub.Nth have the fixed percentages of the updated threshold voltages V.sub.Pnew -V.sub.Nnew.