The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 22, 1997
Filed:
Oct. 03, 1996
Ching-Nan Yang, Jung-He, TW;
Li-Chun Peng, Chu-Dung, TW;
Mosel Vitelic Inc., Hsin Chu, TW;
Abstract
The present invention is a process used for fabricating a CMOS device, which includes (a) forming a first photoresist over the gate conducting layer, (b) define a first gate upon one of the p-type and the n-type MOS regions, (c) executing a first ion implantation in order to form a first lightly doped drain (LDD) on the one of the p-type and the n-type MOS regions, (d) forming a first gate sidewall on the first gate, (e) executing a second ion implantation in order to form a first source and a first drain on the one of the p-type and the n-type MOS regions, (f) forming a second photoresist over the gate conducting layer, (g) eliminating a portion of the second photoresist and another portion of the gate conducting layer in order to define a second gate upon the other one of the p-type and the n-type MOS regions, (h) performing a third ion implantation in order to form a second lightly doped drain (LDD) on the the other portion of the p-type and the n-type MOS regions, (i) selectively forming a specific oxide on the other one of the p-type and the n-type MOS regions, which is not masked by the second gate, (j) removing a portion of the specific oxide in order to form a second gate sidewall on the second gate, (k) executing a fourth ion implantation in order to form a second source and a second drain on the other one of the p-type and the n-type MOS regions, and (l) eliminating a remaining portion of the second photoresist. According to the present invention which can not only reduce the cost and time but also promote the performance of the fabricated CMOS device.