Cache memory system having secondary cache integrated with primary cache

Abstract

A cache memory system with a secondary cache integrated with a direct mapped primary cache in a single structure preferably constructed on a VLSI chip. The secondary cache uses the same output data bitlines, sense amplifiers, and bus drivers as the direct mapped cache. In a first machine cycle, input address tags are simultaneously compared to tag bits in the primary cache and the secondary cache. If the comparison results in a miss in the primary cache and a hit in the secondary cache, the secondary cache data is fed to the microprocessor in the next machine cycle, precluding the need for a main memory access. Thus, allowing data to be read directly from the secondary cache without using an extra machine cycle to load it first into the direct cache. The secondary cache comprises a miss cache which is loaded from main memory with data missing from the primary cache in the first machine cycle. Alternatively, the secondary cache comprises a victim cache which is loaded with a line of the primary cache which is replaced after loading missed data from main memory.