Circuit for designating instruction pointers for use by a processor

Abstract

A circuit designates the values of an M bit first pointer and of an N+M bit second pointer. A first register circuit network holds the M bit first pointer, and a second register circuit network into holds an M bit portion of the N+M bit second pointer. A third register circuit network holds the remaining N bit portion of the N+M bit second pointer. A combiner circuit network, connected to receive the M bit first pointer from the first register circuit network, combines the received M bit first pointer with an externally provided data element length value to generate a new M bit first pointer. The combiner circuit network selectively generates a carry signal. The new M bit first pointer is selectively provided for loading into the first register circuit network and for loading into the second register circuit network as the M bit portion of the N+M bit portion of the second pointer. The remaining N bit portion of the N+M bit second pointer is received from the third register circuit network and, in response to the carry signal, one of the received remaining N bit portion and a modified remaining N bit portion is provided as a new remaining N bit portion for loading the new remaining N bit portion into the third register circuit network.