The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 15, 1997
Filed:
Jul. 31, 1995
William Carl Slemmer, Dallas, TX (US);
SGS-Thomson Microelectronics, Inc., Carrollton, TX (US);
Abstract
According to the present invention, a structure for holding broken select lines in a memory array deselected addresses the prior art problems associated with floating broken select lines, such as standby current and disruption of attached memory cells. The structure is a non-linear, high impedance device which is placed on the end of select lines so that if a select line is broken during fabrication, the non-linear, high impedance device will hold the broken end of the select line to the desired deselect voltage. Select lines which have a driver at one end only and are broken during fabrication, but have the non-linear, high impedance device on the other end, are not allowed to float. The non-linear, high impedance device is also suitable for select lines which are not broken and previously were anchored at just one end. Suitable non-linear, high impedance devices include a reverse biased diode, a weak transistor, a bulk transistor, a poly R memory cell load device, an ON or OFF TFT memory cell load device, or other transistor structures. Additionally, the use of non-linear devices, such as transistor structures, provides the advantage of a compact layout structure that is especially suitable for high density integrated circuit memory devices.