Temporally-pipelined predictive encoder/decoder circuit and method

Abstract

A temporally-pipelined predictive encoder/decoder circuit for encoding or decoding an input signal containing a sequence of data frames received at a particular frame rate and frame data rate into an output signal having an equal frame rate employs a plurality of N predictive encoders/decoders. An input buffer may be used to extract the information for each data frame in the input signal and supply such information to a corresponding one of the encoders/decoders at rate of 1/N of the particular frame data rate. Each encoder/decoder generates corresponding encoded/decoded information as it is received as well as provides digitized frame information to the encoder/decoder processing the next received image frame. The encoded/decoded information is provided to corresponding frame buffers which temporarily store such information. Each one of the frame buffers is connected to respective inputs of a multiplexer, wherein the encoded/decoded information is provided to a multiplexer output to form the encoded/decoded output signal. When information for the entire frame has been stored by a frame buffer, the stored data information is provided to the multiplexer output to provide the portion of the output signal corresponding to that frame.