The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 08, 1997

Filed:

Feb. 22, 1996
Applicant:
Inventors:

Jules D Campbell, Jr, Austin, TX (US);

Rene M Delgado, Austin, TX (US);

Steve Lim, Austin, TX (US);

Assignee:

Motorola, Inc., Schaumburg, IL (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03K / ;
U.S. Cl.
CPC ...
326 81 ; 326 21 ; 326 58 ; 326121 ;
Abstract

An output buffer (30) is connected to an output signal line and receives an internal power supply voltage, for example 3.3 volts, which is lower than a voltage, for example 5 volts, that other devices which may be connected to the output signal line are able to drive. To protect an output transistor (71) from the harmful effects of the higher voltages on the output signal line, the output buffer (30) includes a special bulk biasing circuit (80). The bulk biasing circuit (80) biases the bulk of the output transistor (71) at an internal power supply voltage when the output buffer is driving and when not driving to a voltage determined by the output signal. To prevent overlap currents, the output buffer (30) includes a special gate biasing circuit (100), which momentarily drives the gate of the output transistor (71) to a voltage equal to the internal power supply voltage when the output buffer (30) stops driving.


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