Burst transfers using an ascending or descending only burst ordering

Abstract

Burst ordering logic is used, in an exemplary embodiment, to implement an ascending only burst ordering for cache line fills in 486 computer systems while maintaining compatibility with the conventional 486 burst ordering which uses both ascending and descending burst orders depending upon the position of the requested address (critical Dword) within a cache line (conventional 486 burst ordering is illustrated in Table 1 in the Background). The burst ordering logic (60) implements a 1+4 burst ordering for requested addresses that, for conventional 486 burst ordering, would result in a descending burst order (the exemplary 1+4 burst ordering is illustrated in Table 2 in the Specification). The burst ordering logic includes request modification circuitry (64), address modification circuitry (66), and cacheability modification circuitry (68). If the burst ordering logic detects a cacheable requested address that will cause a cache line fill using an ascending burst order, that requested address is passed through to the bus interface unit for servicing as a normal cache line fill. If, however, the requested address would result in a descending burst order, the cacheability modification circuit modifies cacheability to cause the microprocessor to assert PCD (page cache disable), signaling to the system logic that the requested address is noncacheable--the system logic responds with a single non-burst transfer (1+) of the requested address. The request modification circuitry then signals a burst transfer request for a cache line fill, and the address modification circuitry modifies the requested address to provide a bus cycle address that is within the cache line that contains the requested address but will result in an ascending burst order to transfer that cache line (+4).