The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 01, 1997
Filed:
May. 09, 1994
Yoshimasa Obayashi, Kyoto, JP;
Matsushita electric industrial co. ltd., Osaka-fu, JP;
Abstract
The present invention discloses processor elements interconnected via a network in a parallel computer. The processor element includes a memory unit for storing a program and, per array-variable name, a partitioned array variable, the program being run simultaneously by the processor elements, each partitioned array variable being allocated to respective processor elements, a processor for carrying out a calculation using the partitioned array variable in the memory unit, the partitioned array variable being accessed by being addressed with a variable-name address that includes a code representing an array-variable name, an address converting unit for holding a variable-name address in relation with a physical address on the memory unit for each partitioned array variable to output a corresponding physical address in response to an input of the variable-name address from the processor, a transferring unit for transferring an array variable per array-variable name with the other processor elements via the network, the array variable being transferred to be stored into a free area acquired in the memory unit when a partition direction changes, the free area being as large as a storage area for one partitioned array variable, an address-correspondence updating unit for updating an address correspondence in the address converting unit with a pre-transfer variable-name address in relation with a post-transfer physical address each time the transferring unit completes the transfer per array-variable name.