The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 01, 1997

Filed:

Aug. 10, 1995
Applicant:
Inventors:

Kazuto Furumochi, Kawasaki, JP;

Junji Seino, Kawasaki, JP;

Assignee:

Fujitsu Limited, Kawasaki, JP;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G11C / ;
U.S. Cl.
CPC ...
365226 ; 365227 ; 36518909 ;
Abstract

An object of the present invention is to provide a MOS static RAM in which the power consumption can be reduced when it is required to reduce the power consumption during standby, and sufficient soft error resistance can be secured when it is required to provide sufficient soft error resistance for the cell. AMOS static RAM of the present invention comprises a power supply circuit for generating a plurality of voltages of different voltage values and a selection circuit for selecting one voltage from among the plurality of voltages output from the power supply circuit and supplying the selected voltage as a cell data retention voltage to a flip-flop that forms a cell.


Find Patent Forward Citations

Furumochi, Kazuto. (1997). Mos static ram with improved soft error resistance; high-level supply (U.S. Patent No. 5644546). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/5644546

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

Loading…