The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 01, 1997
Filed:
May. 13, 1996
Stephen W Clukey, South Portland, ME (US);
National Semiconductor Corporation, Santa Clara, CA (US);
Abstract
Device for protecting against circuit-damaging voltage spikes at input nodes and output nodes of electrical circuits and between high- and low-potential power rails. The voltage spikes are of the type identified generally as electrostatic discharges. The device includes a plurality of semiconductor elements, which are preferably bipolar transistors, coupled to the power rails and an input node or an output node of the circuit such that all types of electrostatic discharges can be diverted using the single device of the present invention. In the preferred embodiment of the invention the transistors have a common collector, their bases are open, and they are configured so that the emitter of one transistor is coupled to the high-potential power rail, the emitter of a second transistor is coupled to the low-potential power rail, and the emitter of a third transistor is coupled to the node to be protected. Various combinations of the breakdown characteristics of the several coupled transistors operate to divert all types of voltage spikes, including positive and negative spikes at the node, and positive and negative spikes between the power rails. The device of the present invention is smaller and faster than prior electrostatic discharge protection devices, with sufficient capacity to handle expected transient voltage levels.