Super self-align process for fabricating submicron cmos using micron

Abstract

Submicron channel length FET is fabricated using larger (e.g., 1 micron) design rule fabrication equipment. A polysilicon layer (34) is first formed over an active device region (28). The following transistor elements are then sequentially formed using a single mask opening (38): [1] threshold adjust implant (40) by implanting impurity ions into the active device region surface; [2] LDD implant regions (42) by implanting impurity ions into lower portion of the polysilicon layer (38); and [3] source/drain doped implant regions (44) by implanting impurity ions into the upper portion of polysilicon layer (38). A gate opening (60) is next formed in the polysilicon layer (38) and overlying dielectric layer (57) using large design rule lithography to pattern, and then by etching. Sidewall spacers (66) are formed at a submicron distance apart in the gate opening (60), defining gate length (68) therebetween. LDD doped implant regions (42) and source/drain doped implant regions (44) driven-in from polysilicon layer (38) into the active device region (28), forming LDD regions (72) and source/drain regions (74). A gate oxide (63) is grown between spacers (66) in self-align position. A gate polysilicon contact (80) is formed. Metal gate contact (86) is formed directly above the gate polysilicon contact (80), centered over gate oxide (63), providing centered metal-polysilicon contact (87). Metal source/drain contacts (90) and intermediate isolation layer (84) are formed to complete FET. Submicron FET having a reduced length (112) active device region (28) and/or centered gate metal-polysilicon contact (87) is provided.