Bridge between two buses of a computer system with a direct memory

Abstract

A bridge for interfacing buses in a computer system having an industry standard architecture (ISA) bus and a peripheral controller interconnect (PCI) bus is coupled between the ISA and PCI buses. The bridge has a direct memory access (DMA) control circuit programmable by programming signals to perform a DMA transfer. The DMA has registers for storing base addresses and registers for storing current addresses. The base addresses and the current addresses indicate destinations of transfer data in the DMA transfer. A power management device is coupled to the DMA control circuit and has logic for causing the computer system to enter a suspend mode. A base address register read circuit is coupled to the base address registers. Prior to entering the suspend mode, the base address register read circuit provides one of the base addresses to be read by a central processing unit (CPU) onto disk storage. When the power management device resumes operation of the computer system, the base address that has been read is written back to reprogram the DMA control circuit. The ability to read the base address registers and store base addresses allows a reduction or elimination of shadow registers that shadow every write to a base address register.