Quick resynchronization receiver for sequential decoding of

Abstract

In a digital receiver, convolutionally coded symbol bits are recovered from a received orthogonally modulated signal. The symbol bits are sequentially stored into a memory and each stored symbol bit is read from the memory as specified by a decoding point address into a sequential decoder, which uses a clock pulse as a boundary point of a codeword. If an overflow condition is detected in the memory, the decoding point address is advanced by K bits. If the overflow still exists, it is repeatedly advanced further by K bits. If the overflow is still detected, then the codeword boundary point is shifted by a clock interval. If the overflow continues, the boundary point shifting is repeated. If the boundary point shifting fails to alleviate the problem, then the decoding point address is advanced to a most recent symbol bit and the recovered symbol bits are phase-shifted by 90 degrees. If a suboverflow condition is detected, the decoding point address is advanced to a most recent symbol bit, and the boundary point shifting is again performed and repeated if the suboverflow still exists. If the suboverflow condition still exists after the boundary point shifting is repeated, the decoding point address is again advanced to a most recent symbol bit and the phase timing shift and the codeword boundary point shift are repeated again.