The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 24, 1997

Filed:

May. 31, 1995
Applicant:
Inventor:

Yugo Tomioka, Tokyo, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L / ;
U.S. Cl.
CPC ...
257630 ; 257315 ; 257316 ; 257409 ; 257508 ;
Abstract

A semiconductor device includes a semiconductor substrate of a first conductivity type, a plurality of spaced field-shield isolation structures formed on a surface of the substrate and extending parallelly in a first direction to provide element-forming regions at spaces between every adjacent two of the field-shield element isolation layers, a pair of impurity diffusion layers of a second conductivity type different from the first conductivity type formed in the surface of the substrate at portions adjacent opposite sides of each of the element-forming regions, a plurality of spaced lateral regions defined on the surface of the substrate and extending parallelly in a second direction intersecting with the first direction; and a plurality of discrete gate electrodes formed on the surface of the substrate at portions corresponding to intersections of the lateral and element-forming regions, respectively, in electrically insulated relationship with the substrate, the gate electrodes being aligned along the lateral regions. The semiconductor elements are formed at the intersections, respectively, each semiconductor element having a pair of portions of the impurity diffusion layers disposed at one of the intersection, and a channel region is formed between the portions of the diffusion layers and one of the gate electrodes formed at the one intersection. Also a method of making the semiconductor device includes respective steps of forming the above components constituting the semiconductor device.


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