Compound semiconductor field effect transistor

Abstract

On a semi-insulative GaAs substrate, a n-type GaAs layer, an undoped InGaAs layer, a n.sup.+ -type GaAs layer are grown in order and a SiO.sub.2 layer is deposited thereon. Subsequently, a photoresist layer having an opening at a gate region is formed. With taking the photoresist layer as a mask, side etching is performed for the SiO.sub.2 layer up to the width corresponding to a recess width. With taking SiO.sub.2 layer as a mask, wet etching is performed for n.sup.+ -type GaAs layer. The wet etching is further extended to the intermediate depth position of the undoped InGaAs layer. By lift off method employing the photoresist layer, a gate electrode is formed on the center of the bottom of the recess. A source electrode and a drain electrode are also formed. Thus, since the corner portions of the recess is formed of a material (InGaAs) difficult to cause dislocation, the compound semiconductor field effect transistor can prevent degradation of characteristics in high temperature burn-in test.