Information handling system for transmitting contents of line register

Abstract

An information handling system includes one or more processors, a system bus or network connecting the processors, a memory system connected to the system bus, an asynchronous signal controller connected to the system bus, one or more I/O bridges connected to the system bus, an I/O bus connected to each I/O bridge, one or more devices connected to the I/O bus, including perhaps another I/O-bus-to-I/O-bus bridge where additional devices may be connected to a second I/O bus, wherein the first or host bridge includes remote interrupt control logic having a register wherein an input to each position in the register is from one of the I/O devices downstream from the host bridge, and a shadow register address buffer, both under the control of a sample circuit connected to outputs of the register such that when a change in any register position is detected by the sample circuit, the entire contents of the register are sent to the shadow register indicated in the shadow register address buffer by a processor bypass technique such as the well known direct memory access technique.