Frame buffer interface logic for conversion of pixel data in response to

Abstract

An apparatus for transforming pixel data from a data bus into an expected format for storage in a frame buffer has a first multiplexor, a second multiplexor and a controller. The first multiplexor includes two data inputs coupled to the data bus so that the first data input provides pass-through of received data, and the second data input provides end-for-end byte swapping of bus data. Input selection is made by a byte-swap control signal. The second multiplexor includes an output and four data inputs. The output of the first multiplexor is coupled to each of the four inputs of the second multiplexor so as to provide for end-for-end byte swapping from two of the inputs, end-for-end word swapping from another one of the inputs, and end-for-end half-word swapping from a fourth input. The second multiplexor is responsive to a reorder control signal that alternatively selects one of the first, second, third and fourth inputs of the second multiplexor to be gated to the output of the second multiplexor. The controller generates the byte swap control signal and the reorder control signal. Generation of the byte swap control signal is based on an endian-ness characteristic of the data bus. Generation of the reorder control signal is based on a pixel depth of pixel data on the data bus and is based further on a pixel endian-ness type of pixel data on the data bus.