The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 17, 1997

Filed:

Sep. 27, 1995
Applicant:
Inventor:

Michio Shimada, Tokyo, JP;

Assignee:

NEC Corporation, Tokyo, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H04K / ;
U.S. Cl.
CPC ...
380 42 ; 380 28 ; 380 49 ;
Abstract

ELT transformation circuits 101.sub.1 to 101.sub.m are preliminarily supplied with ELT transformation parameters a.sub.i, b.sub.i, and p.sub.i (i=1, 2, . . . , m). When a plaintext of n bits long is supplied to the ELT transformation circuit 101.sub.1 via an input terminal 104, the ELT transformation circuit 101.sub.1 carries out ELT transformation on the plaintext by the use of ELT transformation parameters a.sub.1, b.sub.1, and p.sub.1 supplied from an input terminal 105.sub.1. An enciphering circuit 102.sub.1 enciphers an n/2-bit input with reference to a cryptographic key K.sub.1 from an input terminal 106.sub.1. Supplied with two n-bit inputs, an exclusive-OR circuit 103.sub.1 carries out an exclusive-OR operation between every corresponding bits of the same order. Subsequently, similar operation as mentioned above is repeated. The ELT transformation circuit 101.sub.m at a final stage delivers a ciphertext to an output terminal 107.


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