The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 17, 1997

Filed:

Nov. 09, 1995
Applicant:
Inventors:

Katsuaki Abe, Kawasaki, JP;

Masahiro Mimura, Tokyo, JP;

Makoto Hasegawa, Tokyo, JP;

Kazunori Watanabe, Yokohama, JP;

Katsushi Yokozaki, Yokohama, JP;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H03D / ; H04L / ;
U.S. Cl.
CPC ...
375334 ; 375328 ;
Abstract

In a first direct conversion receiver for demodulating I and Q signals, having a quadrature relation therebetween, obtained from a received FSK signal through a direct conversion, a first D FF latches a level of the I signal when a sign condition of I and Q signals moves from the same to different sign conditions, a second D FF latches a level of the Q signal when the sign condition of the I and Q signals moves from the different to same sign condition and EXCLUSIVE OR operations are made among the I and Q signals and the outputs of the first and second D FFs to provide a frequent data judgement to improve a receiving sensitivity of an FSK signal having a relative low modulation index. In a second direct conversion receiver, a sign change in the Q signal is detected by a first edge detection circuit 17, a first D FF holds the level of the I signal, and an EXCLUSIVE OR circuit provides a first demodulation result. A sign change in the I signal is detected by a second edge detection circuit 17, a second D FF holds the level of the Q signal, an EXCLUSIVE OR circuit provides a second demodulation result and a subtracting circuit combines the first and second demodulation results. An earlier change detection circuit also combines the first and second demodulation results with a delay in the first and second demodulation results reduced.


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