Direct downconverter circuit for demodulator in digital data

Abstract

A digital downconverter circuit for a digital data transmission system is provided, comprising (i) a bandpass filter circuit for filtering a received analog intermediate frequency (IF) carrier signal onto which baseband information has been modulated, and outputting a bandpass analog IF signal; (ii) an analog-to-digital converter for converting the bandpass analog IF signal into a bandpass digital IF signal; (iii) a phase shifter device for outputting a complex pair of phase shifted baseband signals operating at a local baseband frequency; (iv) a mixer device for mixing the bandpass digital IF signal separately with each of the complex pair of phase shifted baseband signals and outputting a complex combined baseband/bandpass signal comprising inphase and quadrature components; (v) filtering circuitry for recovering the baseband information onto the phase shifted baseband signals; and (vi) sampling circuitry for sampling the information-bearing recovered baseband signals and outputting a sampled complex baseband output signal. The phase shifter device, the mixer device, the filtering circuitry, and the sampling circuitry are all implemented on a gallium arsenide (GaAs) application specific integrated circuit (ASIC). The filtering circuitry includes a single half-band pre-filter and a multi-pole low pass filter. The analog-to-digital converter operates at the sampling clock frequency, which is about 512 megahertz (MHz), and the IF carrier signal operates at about 52-176 MHz. An automatic gain control circuit controls the amplitude of the bandpass analog IF signal prior to its being converted into the bandpass digital IF signal.