Burst transmission semiconductor memory device

Abstract

A semiconductor memory device includes a burst decode signal generation circuit including a bi-directional loop shift register, an input register corresponding to configuration bits outputted from the first first-order decoder, in which the register captures the corresponding configuration bits, so as to subject each of the configuration bits outputted from the first first-order decoder to a circulation shift by synchronizing with the internal address progress clock in a predetermined direction in accordance with an initial address of the first bits of the address signals, and an initial address even/odd judgment section for judging whether the initial address is even or odd, a plurality of input registers, each of which captures decoded signals outputted from the second first-order decoder in an initial value capturing internal clock, a main decoder which decodes outputs from the input registers and the burst decode signal generation circuit for subsequent output of address selective signals, and a memory cell array section which shows read/write operations of data at an address selected in accordance with the address selective signal.