The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 17, 1997

Filed:

Feb. 15, 1996
Applicant:
Inventors:

Tomoaki Yabe, Kawasaki, JP;

Shinji Miyano, Yokohama, JP;

Katsuhiko Sato, Yokohama, JP;

Kenji Numata, Yamato, JP;

Assignee:

Kabushiki Kaisha Toshiba, Kawasaki, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C / ;
U.S. Cl.
CPC ...
36518904 ; 36518905 ; 36523006 ; 36523008 ;
Abstract

According to the present invention, a data bus common to a plurality of memory cell arrays is formed by selecting a column so as to prevent a data collision from occurring. Specifically, two memory cell arrays have each of data buses in common. A column decoder is supplied with a control signal to control a column selection logic circuit. The column selection logic circuit is so controlled that the data read out to the data buses in response to the control signal is prevented from colliding with each other during the simultaneous access to the two cell arrays.


Find Patent Forward Citations

Yabe, Tomoaki. (1997). Semiconductor memory circuit having data buses common to a plurality of (U.S. Patent No. 5640351). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/5640351

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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