The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 17, 1997

Filed:

Mar. 14, 1996
Applicant:
Inventors:

Jin Hwan Lee, Daejeon, KR;

Chie Teuk Ahn, Daejeon, KR;

Joo Hong Jeong, Daejeon, KR;

Sang Gyu Park, Daejeon, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H04N / ;
U.S. Cl.
CPC ...
348445 ; 348454 ;
Abstract

An NTSC/PAL video signal conversion apparatus employing a ITU-R BT.601 video signal, comprising a timing reference signal decoder for detecting a timing reference signal from external input data in response to an external clock signal, a counting circuit for performing a plurality of counting operations in response to output signals from the timing reference signal decoder and the external clock signal, a write address generator for generating a write address, a write enable signal and a chip enable signal in response to output signals from the counting circuit, a read address generator for generating a read address, a read enable signal and a chip enable signal in response to the output signals from the counting circuit, a first multiplexer for selecting one of the write address from the write address generator and the read address from the read address generator in response to the external clock signal, a first D flip-flop for latching the external input data, a memory for storing output data from the first D flip-flop, a second D flip-flop for latching output data from the memory, a timing reference signal generator for decoding the output signals from the counting circuit, and a second multiplexer for multiplexing an output signal from the timing reference signal generator and output data from the second D flip-flop.


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