The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 17, 1997

Filed:

Dec. 01, 1994
Applicant:
Inventors:

Osamu Koseki, Chiba, JP;

Takichi Ishii, Chiba, JP;

Masaaki Mandai, Chiba, JP;

Tomoyuki Yoshino, Chiba, JP;

Hitoshi Takeuchi, Chiba, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L / ;
U.S. Cl.
CPC ...
437209 ; 437211 ; 437214 ; 437217 ; 437218 ;
Abstract

A process for fabricating a semiconductor device which permits the placement of plural semiconductor chip devices at a reduced pitch comprises the steps of bonding a plurality of semiconductor chip devices to a substrate, forming a conductive thin film on the substrate to cover at least connecting regions of the semiconductor chip devices, and patterning the conductive thin film using an excimer laser to form interconnections between the respective semiconductor chip devices. The conductive thin film is formed by a method selected from physical vapor deposition and chemical vapor deposition. The step of bonding the semiconductor chip devices to a substrate is preferably performed using an epoxy-based adhesive. Preferably, an insulating film is formed on the plural semiconductor chip devices in regions except for the connection regions. Patterning of the conductive thin film is performed using an excimer laser beam emitted in two pulses at an output energy of 300 mJ/cm.sup.2.


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