The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 10, 1997

Filed:

Jan. 04, 1993
Applicant:
Inventor:

Toshiaki Ueda, Kanagawa-ken, JP;

Assignee:

Kabushiki Kaisha Toshiba, Kawasaki, JP;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F / ;
U.S. Cl.
CPC ...
364491 ; 395800 ; 364490 ; 364148 ;
Abstract

A method for automatically optimizing cell placement on a chip using many processors. In the method, the chip is divided into first regions along a first direction. In each first region, a cell is moved in only one direction, which is perpendicular to the first direction. This operation for each first region is executed at the same time by each processor. After an evaluation function is calculated for each first region, the optimized evaluated value for each first region is stored in a memory in each processor. Next, the chip is divided into second regions along a second direction which is vertical to the first direction. The second regions are moved in only one direction which is perpendicular to the second direction. In the same manner that the first regions are processed, the second regions are similarly processed. Thus, an optimizing cell placement can be obtained.


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