The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 10, 1997
Filed:
Apr. 06, 1995
Applicant:
Inventors:
Arnold Ginetti, Antibes, FR;
Christophe Gauthron, La Colla sur Loup, FR;
Assignee:
VLSI Technology, Inc., San Jose, CA (US);
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F / ; G01R / ;
U.S. Cl.
CPC ...
364489 ; 364488 ; 364490 ; 364580 ; 371 222 ; 371 251 ; 371 28 ; 29847 ; 29850 ;
Abstract
A method for removing the critical false paths takes place during logic optimization. It is based on a path-constrained redundancy removal algorithm. This path-constrained redundancy removal algorithm automatically finds that a path node does not affect the behavior of the path output and so determines a critical path. This method is iteratively repeated for as long as this critical path is false.
Ginetti, Arnold. (1997). Method for eliminating a false critical path in a logic circuit (U.S. Patent No. 5638290). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/5638290
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