The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 10, 1997
Filed:
Aug. 24, 1994
Richard Deeley, San Jose, CA (US);
LSI Logic Corporation, Milpitas, CA (US);
Abstract
On integrated circuit designs employing large, pre-defined circuit blocks, chip area utilization and signal routing is improved by permitting signals between circuit blocks surrounding (e.g., on opposite sides of) a large circuit block (megacell) to physically pass through the megacell. The megacell is laid out so that a 'parting line' is defined through the megacell. Circuits within the megacell are laid out so that no circuit 'straddles' the parting line. The megacell can then be split or stretched about the parting line to create a wiring channel. The wiring channel is used for routing signals from the surrounding cells (circuit blocks) through the large circuit block (megacell). Signals between the separated portions of the stretched or split megacell on opposite sides of the parting line may be routed in one metal layer, while connections of surrounding cells through the megacell may be routed in another metal layer. A maximum split or stretch distance is defined for which the megacell performance specifications (e.g., timing constraints) will be met. A plurality of surrounding cells may be interconnected by routing their signals in stacked wiring layers. The megacell may be split or stretched about two or more parting lines to create two or more wiring channels.