Method for testing a nonvolatile semiconductor memory device

Abstract

A method for testing nonvolatile memory device includes the steps of forming a block including a test row and a first and a second decoding row, by connecting the sources of the memory cells in the test row together to form a common source line, connecting each column of memory cells in the three rows in series, connecting the drains of the memory cells in the second decoding row together to form a common drain line, erasing the memory cells in the first and second decoding rows, successively programming and erasing the memory cells in the test row, and measuring a first drain current flowing through the common drain line with respect to the voltage of the word line of the test row. If the first drain current exhibits a negative threshold voltage, an over-erased memory cell exists in the test row. Thereafter, the total drain current of the memory cell other than the over-erased memory cell and the drain current of the over-erased memory cell can be separately measured for analyzing the tunnel oxide film of the memory cells.