The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 03, 1997
Filed:
Mar. 07, 1995
Gary A Brown, Fremont, CA (US);
National Semiconductor Corporation, Santa Clara, CA (US);
Abstract
An analog-to-digital converter (ADC) voltage offset (VOS) reduction circuit architecture is for use with an ADC that includes a resistive ladder network and a differential-to-single ended converter. The DC level of the single-ended output of the differential-to-single ended converter is nominally set at the mid-point of the resistive ladder network. The VOS reduction circuit includes a VOS comparator bank that receives the single-ended output, compares it with a plurality of input signals from the resistive ladder network, and provides the result of the comparison as a plurality of VOS comparator bank signals. A current digital-to-analog converter (IDAC) is coupled to receive the VOS comparator bank signals, via a latch bank, and to provide a current responsive thereto. The current from the IDAC may be provided as a trim current for adjusting the DC level of the single-ended output of the ADC differential-to-single ended converter to be closer to the mid-point of the resistive ladder network, thus reducing voltage offset caused, for example, by variations in process and temperature.