The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 03, 1997
Filed:
Jun. 03, 1996
Applicant:
Inventors:
Pantas Sutardja, San Jose, CA (US);
Sehat Sutardja, Cupertino, CA (US);
Assignee:
Marvell Technology Group, Ltd., Sunnyvale, CA (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03B / ;
U.S. Cl.
CPC ...
331 57 ; 331115 ; 331132 ; 331135 ; 3311 / ;
Abstract
A monolithic CMOS phase-lock loop (PLL) circuit provides a high frequency of operation suitable for RF applications. The PLL produces an output clock with high spectral purity and very low jitter. The output clock has a low static phase error relative to a reference input, making the PLL also useful for clock synchronizing applications, such as clock recovery elements in transmission/recycling channels. The PLL provides in-phase and quadrature signals from a VCO which has two differential transconductor stages having negative output conductance.