The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 03, 1997

Filed:

May. 15, 1995
Applicant:
Inventor:

Victor P Seidel, Burlington, VT (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G01R / ; G01R / ;
U.S. Cl.
CPC ...
324754 ; 324755 ; 324761 ;
Abstract

According to the present invention an improved device and method for testing the integrity of electrical connectors on a substrate and/or for providing for burn-in of a semi-conductor on a substrate is provided. The test unit includes a mounting fixture having a plurality of pins carried thereon preferably spring loaded. At least some of the pins are provided with a plurality of circumferentially spaced conducting members which are electrically insulated from each other. These pins are configured and mounted on the fixture to move into and out of engagement with a portion at least two and preferably four adjacent connectors on the substrate thereby allowing a single pin to contact up to four or more contacts on the substrate. In addition to the single pin contacting four or more connectors, the pins are configured such that they fit between the connectors rather than resting on top of them with the electrically conducting members contacting the sides of the solder balls thereby providing a extended contact surface as opposed to contacting the tops of the connectors on the substrate. Each of the separate conducting members on the pins is connected to a test circuit and/or a burn-in circuit which provides the appropriate test signals and/or power to the various connectors on the substrate.


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