Cache memory system for multiple processors with collectively arranged

Abstract

A cache memory system capable of realizing a high level performance and a high speed processing with a simple control. The system may use a plurality of processing units and a plurality of corresponding cache memory units, where all the cache tag memory units of the cache memory units are collectively arranged in relation to the primary processing unit which carries out a memory access address calculation. The system may also use a refilling control such that a new refilling operation for a newly occurred cache miss in the primary cache memory unit is started in parallel to another refilling operation for a previously occurred cache miss in the primary cache memory unit before that another refilling operation is completed. The system may also use a refilling control such that the refilling operation is started by making an access to the secondary memory unit with a starting address at which the cache miss occurred in the primary cache memory unit, and continued by making subsequent accesses to the secondary memory unit with addresses obtained by adding an increment to the starting address one by one.