Method of forming p-type islands over p-type buried layer

Abstract

A method of fabricating a vertical conductive region in a semiconductor device in which plural epitaxial layers are successively grown on a substrate and a dopant is implanted into each epitaxial layer before growing the next layer. A fast vertical transistor operable in the GHz range and at high voltage (e.g., more than about 10 volts) is fabricated by growing plural epitaxial layers, each with a thickness less than about 2.5 microns until the desired height of the vertical conductive region is reached. Sections of the transistor's collector and an adjacent sinker are implanted through each epitaxial layer before the next layer is grown. Annealing after ion implant joins the sinker and collector sections in each layer with the corresponding sinker and collector sections in adjacent layers to form unitary structures in the transistor. Each layer is thin enough for the dopant to penetrate to the bottom of the layer using conventional implant energy. The manufacturing process does not limit the height of the sinker or collector.