The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 20, 1997

Filed:

Jan. 24, 1995
Applicant:
Inventors:

Richard E Walker, The Woodlands, TX (US);

Kurtis J Bowman, Cypress, TX (US);

Assignee:

Compaq Computer Corporation, Houston, TX (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F / ;
U.S. Cl.
CPC ...
395750 ; 326 68 ;
Abstract

A circuit that automatically switches the power supply voltage PVDD provided to a CPU between 3.3 volts and 5 volts. The circuit detects whether the CPU installed in a socket is a 3.3-volt part or a 5-volt part by determining the state of a voltage detect sense pin provided by the socket. If the voltage detect sense pin is driven low, that indicates a 3.3-volt CPU is being used. If a 5-volt CPU is installed, the voltage detect sense pin is left floating by the CPU, which allows a pullup resistor to pull the voltage detect sense pin high. The power supply voltage provided to the CPU is regulated through a power field effect transistor (FET). The gate of the power FET is connected to the output of a voltage reference source and is coupled to a 12-volt supply signal. If the voltage detect sense pin is pulled high, the voltage reference source is turned off, allowing the 12-volt supply signal to drive the gate of the power FET. This in turn allows the power FET to pass a 5-volt supply signal to the CPU supply signal PVDD. If the voltage detect sense pin is pulled low, the voltage reference source is turned on to drive the gate of the power FET to approximately one threshold voltage above 3.3 volts. In response, the power FET passes only 3.3 volts to the CPU supply signal PVDD.


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