The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 20, 1997
Filed:
Aug. 12, 1993
Masahisa Narita, Hitachi, JP;
Hisashi Kaziwara, Hitachi, JP;
Takeshi Asai, Hitachi, JP;
Shigeki Morinaga, Hitachi, JP;
Hiroyuki Kida, Kokubunji, JP;
Mitsuru Watabe, Katsuta, JP;
Tetsuaki Nakamikawa, Hitachi, JP;
Shunpei Kawasaki, Tokyo, JP;
Junichi Tatezaki, Kodaira, JP;
Norio Nakagawa, Koganei, JP;
Yugo Kashiwagi, Bloomington, IN (US);
Hitachi, Ltd., Tokyo, JP;
Hitachi Engineering Co., Ltd., Ibaraki-ken, JP;
Abstract
A multiplication, division and square root extraction apparatus which calculates the solutions to addition, division and square root extraction functions by approximation using iteration has a multiplier, an adder-subtracter and a shifter of prescribed bit width connected to a bus. Iteration is conducted by inputting the output of the multiplier to the adder-subtracter or the shifter and returning the result to the input of the multiplier via the bus. A shifter and an arithmetic and logic unit connected to a second bus connected to the aforesaid bus via a switch have a greater bit width than the prescribed bit width and are used for large scale calculations, thus preventing a reduction in processing speed.