The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 20, 1997

Filed:

Oct. 14, 1994
Applicant:
Inventors:

Yachin Afek, Kfar Saba, IL;

Claudine Tordjman, Holon, IL;

Ricardo Berger, Raanana, IL;

Assignee:

Motorola, Inc., Schaumburg, IL (US);

Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H03B / ;
U.S. Cl.
CPC ...
327108 ; 327374 ;
Abstract

A transition control circuit (2) for controlling the transitions of an output signal, at an output node (8) of a driver circuit, in dependence on the logic state of an input signal at an input node (10). The output signal being switchable between a first logic state and a second logic state. The transition control circuit (2) comprises first means (16) and second means (14). The first means (16) is enabled when the output signal has the first logic state and the input signal has the second logic state, and is disabled when the output signal has the second logic state or the input signal has the first logic state. Once enabled, the first means (16) couples the output node (8) to a first supply line (GNDA) whereby the output signal switches to the second logic state. The second means (14) is enabled when the output signal has the second logic state and the input signal has the second logic state, and is disabled when the output signal has the first logic state or the input signal has the first logic state. Once enabled, the second means (14) couples the output node to a second supply line (GNDB) whereby the output signal is held in the second logic state until the next transition of the input signal.


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