Solid state array with supplemental dielectric layer crossover structure

Abstract

A solid state array device includes a plurality of pixels with associated respective TFT switching transistors; a plurality of first address lines disposed in a first layer of the array device; a plurality of second conductive address lines disposed in a second layer of the array device, respective ones of said first and second address lines being disposed substantially perpendicular to one another in a matrix arrangement such that respective ones of the second address lines overlie respective ones of the first address lines at respective crossover regions; a TFT gate dielectric layer disposed in a channel region of each of the pixel TFTs and further being disposed over the first address lines; and a crossover region supplemental dielectric layer disposed in respective ones of the crossover regions between the first and second address lines, but disposed so as to not extend over the TFT channel regions.